HDL Works HDL Design Entry EASE 8.0 R8

EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You dont need to be a master of either Verilog or VHDL. When youre creating a new design, just enter your design using  your mix of graphics and text. EASE automatically generates optimized  HDL code for you in the selected language - VHDL or Verilog. Industry  standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on one EASE  project.

Features  Benefits

- Graphical design environment with automated generation of hierarchical VHDL or Verilog code 

- Push-button import of legacy Verilog or VHDL designs and extraction of graphical hierarchy 

- Adheres to state of the art Windows look and feel for intuitive operation 

- Standards compliant (IEEE-1076-87 93 VHDL and IEEE-1364 Verilog) 

- True multi-user design environment and associated version control, managed by a sophisticated design environment browser 

- Integrates smoothly with the industrys most popular simulators and synthesis tools 

- Platform independent database 

- Integrated HDL language editor 

- Hot error reporting

Project Browser

The  Project Browser provides a good overview and offers easy access to the  design elements. The browser offers three views: the Database View shows  a tree of all elements in your project, the File View shows all HDL  files in the project and their status and the Hierarchical View shows  the HDL hierarchy of your project. It also provides many status details  of the different objects, like verification status, 'instantiated from'  info, version number and more. From the browser, all objects can be  opened in their respective editor (block, state, truth table or text  editor).

The  Hierarchical View shows the hierarchy on the selected entity, module or  configuration. It allows you to create or delete configurations. Here  you can also changes the binding of an architecture to a component when  having multiple architectures for an entity. 

Block Diagram Editor

The  block diagram editor allows you to easily decompose your system into  functional blocks. It is up to you how detailed you want to make the  decomposition. Each block can be implemented using one of the four  available editors. Facilitating an abstraction level between block  diagrams and plain HDL code, the block diagram editor allows you to  graphically represent VHDL processes or Verilog always statements. They  can be implemented using state diagrams, truth tables or HDL text. This  approach visualizes the data flow inside a single diagram.

State Diagram Editor

The  state diagram editor supports Moore, Mealy and mixed state machines.  Any valid VHDL expression or Verilog statement can be used to define  actions and transition conditions. Transitions can be synchronous or  asynchronous; outputs can be clocked or combinatorial. The state diagram  editor supports a variety of state assignment methods, including  binary, gray, one-hot and two-hot. User defined assignment is also  supported. The generated HDL is optimized for time and area to achieve  the best possible synthesized design from leading synthesis tools.

Truth Table Editor

The  truth table editor is useful for decoders and decision logic. The  spreadsheet like editor in combination with a flexible and smart use of  column headers allows a compact visualization of the intended behavior. A  column-fill wizard is available to generate data in various encoding  styles and representations.

Scriptum - Internal Text Editor

EASE  comes complete with its own integrated HDL language editor, Scriptum.  Even on extremely large files Scriptum offers exceptionally fast editing  capabilities. You can avoid typing errors and dramatically improve your  productivity by using keyword and header templates, identifier repeat,  auto case conversion and one-touch line and column manipulation. To keep  your text highly readable and well structured, you may choose syntax  coloring and in- and out-commenting of selected text, as well as line  numbering and indentation. Scriptum offers extensive documentation  capabilities such as color coding, capitalization and indentation to  make your numerous lines of code more readable. Scriptum is fully  customizable to create a design environment that meets your needs.  Design language, synthesis templates, keyword templates, and user  interface are easily tailored to your requirements.

Integrating external HDL

External  HDL files like IP, legacy code, Matlab code and FPGA generated models  can be integrated in your project as external objects. EASE will create  symbols and component declarations for instantiated modules. Symbols can  be easily updated to the latest version of your code. Existing HDL can  also be translated into block diagrams. Symbol libraries for FPGA  primitives can be created on the fly from vendor VHDL or Verilog  descriptions. 

Verification and Linting

Before  VHDL or Verilog is generated EASE verifies the design for  inconsistencies and syntax errors. Linting is an additional verification  effort to find potential design problems (like range mismatches in  assignments of vectors, or read-only signals) and optimizes the design  by identifying unused signals and definitions. Errors, warnings and  notes are reported in the verification pane. The messages are hot-linked  to the corresponding editor to quickly navigate to the offending code.

Many  FPGA's and ASIC's are designed by a team of engineers that need to work  closely together to finish the implementation correct and on time. The  best way to work together on a project is by using a design environment  that allows a group of designers to simultaneously work on the project  without interfering with each other. EASE supports team based design  using industry standard version management systems like RCS, CVS,  ClearCase and Subversion. All designers in the team can  check-in/check-out objects at the entity/module level. This fine grain  control allows you to edit the parts that you need to work on while your  colleagues can still read these parts. 

3rd Party Interfacing

EASE  has a user configurable third party tool flow interface. A wizard will  help the user to select the appropriate tools and set the options for  these tools. Extra tool buttons will be added to the GUI for easy access  to the selected tools. A list of tools supported by default is provided  below. Other tools or vendors are easily added through the Tcl  interface. 

Simulation tools:

- ModelSim (Model Technology's )

- NCSim, Verilog-XL (Cadence)

- Xilinx ISIM

- Silos (Silvaco)

- Riviera (Aldec)

- VCS (Synopsys)

Synthesis tools:

- Altera Quartus

- Synplify (Synplicity)

- Precision

- Xilinx ISE

The FPGA Vendor tools from:

- Actel

- Altera

- Xilinx

HTML Generator

The  HTML Generator allows you to export the whole project on your intranet  or to the internet. With a single click EASE will export all diagrams,  side data, generated HDL code and the project structure to the desired  location in HTML and SVG files. SVG (Scalable Vector Graphics) is the  W3C standard XML-based imaging model started by Adobe. Graphics created  in SVG can be scaled without loss of quality across various platforms  and devices. The exported HTML contains hot links in the diagrams and  the project structure to easily navigate through your design. 

Standards Support

EASE's  code generator produces HDL output conforming to IEEE-1076-87 and  IEEE-1076-93 VHDL standards, as well as the IEEE-1364 Verilog standard.  EASE also supports the industry's leading simulators and synthesis  tools, as well as version control features when provided.

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